Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
Flash memory devices typically use a floating gate, one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. The adjustment of the charge on the floating gate determines a threshold voltage (Vt) for the cell and, therefore, the programmed/erased state of the cell. For example, when the memory cell has a negative threshold, it has a logical “1” state. When the threshold is positive, the cell has a logical “0” state. Typically, an erased memory cell is at a logical “1” state.
In order to reduce the price per bit, memory manufacturers have created multi-level flash memory cells that are capable of storing multiple bits per cell. When one memory cell stores “n” bits of data, the memory cell has 2n states or 2n threshold voltage levels. For example, if a memory cell stores two data bits, the cell has four threshold voltage (Vt) bands.
Two common types of flash memory array architectures are the “NAND” and “NOR” architectures. These architectures are named for the resemblance that the basic memory cell configuration of each architecture has to a basic NAND or NOR gate circuits, respectively.
Flash memory devices are programmed and erased by sequences of operations. A program operation typically involves sequentially applying a programming pulse and a program-verify read pulse to a block of memory cells of the device. The programming pulse/read operation is repeated, with the programming pulse increasing incrementally each time, until the cells are programmed.
An erase operation typically comprises a pre-programming cycle, an erase cycle, and a soft program cycle. The pre-programming cycle puts the memory cell into a known programmed state by applying a program pulse to each row of memory cells in the memory block. The erase cycle removes charge from the floating gate to make it more negative. The soft program cycle corrects the cell for over-erasure after the erase cycle has been completed. By applying a programming pulse that has a lower amplitude than a normal programming pulse, the threshold voltage for the over-erased cell is brought back to an appropriate level.
FIG. 1 illustrates a block diagram of a typical prior art flash memory device. Such a device is comprised of a memory array 101 for storing data. The memory array 101 is comprised of a plurality of memory cells, as described previously, that are connected in a row and column format. The rows of cells are coupled by word lines and the columns are coupled by bit lines.
A data cache 103 is coupled to the array 101 and temporarily stores data to be written into the array 101 and data that has been read out of the array 101. The data in/out block 105 is the control circuitry for controlling the reading and writing of in and out of the array 101.
A fuse area 106 in a non-volatile area of memory for storing memory parameters that concern chip behavior. These parameters can include memory block lock commands, voltages, timing, and other such types of parameters. The analog block 108 is responsible for generating the various voltages required for integrated circuit operation. For example, the writing and erase operations require different voltages be applied to the various selected and unselected word lines and bit lines.
A command state machine (CSM) 112 is coupled to an algorithm controller 110 and interprets user commands that are entered through the integrated circuit pads 114. The algorithm controller 110 is typically a state machine or processor that generates the control signals and signal sequences for the read, program, and erase operations in response to the interpreted commands from the CSM 112. The controller 110 also controls the generation of the analog voltages from the analog block 108.
The flash memory device control circuit 110 manages the various components of the flash memory by performing the above-described memory operations. The controller interacts with hardwired actuators to send actuator signals to analog voltage generators of the memory device for controlling the voltage generators during program, erase, and other memory operations.
One problem with these controllers and hardwired actuators is that they are a fixed design for a particular application. The circuits cannot be readily reconfigured or updated for other applications. This limits the flexibility of the flash memory device.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for memory controller circuitry that can be adapted to different applications.